Conventionally, in a liquid crystal display device adopting an a-SiTFT liquid crystal panel (a liquid crystal panel using amorphous silicon for semiconductor layers of thin film transistors), since the mobility of amorphous silicon is relatively small, a gate driver for driving gate bus lines (scanning signal lines) is mounted in an area around a substrate composing a panel, as an IC (Integrated Circuit) chip. However, in recent years, in order to achieve miniaturization, a reduction in cost, etc., of the device, formation of a gate driver directly on a substrate has been done. Such a gate driver is called a monolithic gate driver, etc. A panel including a monolithic gate driver is called a gate driver monolithic panel, etc.
FIG. 21 is a diagram showing an exemplary layout of a gate driver (monolithic gate driver) in a conventional liquid crystal display device adopting a gate driver monolithic panel. As shown in FIG. 21, the gate driver includes a shift register configured by a plurality of stages for sequentially driving a plurality of gate bus lines (scanning signal lines) arranged in a display unit; and wiring lines that transmit clock signals, etc., for allowing the shift register to operate. Each stage of the shift register is a bistable circuit which is in either one of two states (a first state and a second state) at each time point and outputs a signal indicating the state (state signal) as a scanning signal through an output transistor (a transistor connected at its one conduction terminal to a scanning signal output terminal and controlling the potential of the state signal by changing the potential at a control terminal of the transistor). Note that FIG. 21 only shows a layout of two stages of the shift register. For wiring lines, there are formed, on a substrate, drive signal trunk wiring lines that transmit clock signals CK1, CK1B, CK2, and CK2B and a clear signal CLR for initializing the state of each bistable circuit; a VSS trunk wiring line that transmits a low-level direct-current power supply potential VSS; and branch wiring lines that connect the drive signal trunk wiring lines and the VSS trunk wiring line to each bistable circuit. Note that in the following a region where the shift register is formed is referred to as a shift register region, a region where trunk wiring lines for the drive signal and VSS are formed is referred to as a trunk wiring line region, and a region corresponding to the display unit is referred to as a display region.
Meanwhile, in general, when a circuit is formed, a circuit portion is arranged to be adjacent to an input portion, and an output portion is arranged to be adjacent to the circuit portion. In the conventional monolithic gate driver, too, as shown in FIG. 21, the trunk wiring line region corresponding to the input portion is provided to be adjacent to the shift register region, and portions corresponding to the output portions and indicated by reference character 90 are also provided to be adjacent to the shift register region. Such an arrangement is common and the trunk wiring lines for various signals are collectively formed in the above-described trunk wiring line region. In the configuration shown in FIG. 21, taking a look at a specific arrangement of each wiring line, the drive signal trunk wiring lines and the VSS trunk wiring line are formed in a region on the opposite side of the display region with respect to the shift register region. Taking a look at a positional relationship between the drive signal trunk wiring lines and the VSS trunk wiring line, the region where the VSS trunk wiring line is formed is closer to a panel edge portion than the region where the drive signal trunk wiring lines are formed. In addition, in the example shown in FIG. 21, the VSS trunk wiring line and the branch wiring lines are formed in the same layer, and the drive signal trunk wiring lines and the branch wiring lines are formed in different layers. Hence, a drive signal trunk wiring line and a branch wiring line are connected to each other through a contact.
Note that in connection with an invention of this matter, the following prior art documents are known. Japanese Patent Application Laid-Open No. 2006-79041, Japanese Patent Application Laid-Open No. 2007-316642, and Published Japanese Translation of PCT Application No. 2005-527856 disclose examples of a layout of two stages of a shift register in a gate driver. In particular, FIG. 2 of Japanese Patent Application Laid-Open No. 2006-79041 and FIG. 6 of Published Japanese Translation of PCT Application No. 2005-527856 disclose examples of a layout where trunk wiring lines are configured such that the widths thereof become narrower as they approach a shift register region from a panel edge portion.